Develop solutions for all aspects of Physical Design migration and verification for full custom digital and analog design. Implementation and development/automation of tasks for full chip physical design migration in addition to new methodology development and vendor tool evaluations and integration.
- 2-3 years hands-on-experience with physical migration (automatic layout modification) from process to process
- Experience with Sagantec tools like SiClone, SiFix a plus
- Knowledge of mask layout design
- Expertise in physical verification (DRC, LVS, ERC) a plus
- Knowledge of C/C++, UNIX and Perl scripting languages
- Knowledge of Cadence/Skill, Calibre, Hercules a plus
- Good interpersonal & communication skills
Requires BSEE and 2 years experience or MSEE
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Develop solutions for all aspects of VLSI physical design and verification for full custom digital and analog blocks and full chip. Perform development and validation of verification decks such as DRC (Design Rule Checking), LVS (Layout Versus Schematic), ERC (Electrical Rule Checking). Provide verification support for both full chip and block designers and develop infrastructures to automate the verification steps.
- 2 or 3 years hands-on experience with verification tasks such DRC, LVS and ERC.
- Experience in run set development with Synopsys Hercules tool or Mentor Graphics Calibre tool a plus
- Knowledge of mask layout design
- Knowledge of Cadence/Skill a plus
- Knowledge of C/C++, UNIX and Perl scripting languages
- Good interpersonal & communication skills
Requires BSEE and 2 years experience or MSEE
Develop solutions for all aspects of VLSI physical design and extraction for full custom digital and analog blocks and full chip. Perform development and validation of extraction decks such as LPE (Layout Parasitic Extraction). Provide verification support for both full chip and block designers and develop infrastructures to automate the extraction steps including back annotation.
- 2 or 3 years hands-on experience with one or more of the following LPE tools: Star_RCXT, Calibre-XRC, quickcap, Raphael
- Good understanding of ASIC design flow, layout generation, circuit simulation, device physics and modeling. Familiar with up-to-date foundry process especially for BEOL.
- Experience with LVS a plus
- Experience with Cadence/Skill a plus
- Knowledge of C/C++, UNIX and Perl scripting languages
- Good interpersonal & communication skills as this position requires extensive interaction with internal design team, verification teams and external tool vendors.
Requires BSEE and 2 years experience or MSEE
Responsible for the infrastructure for rolling out new tools and flows and provide physical design and verification/extraction support and address requirements from customers (layout designers, circuit designers and tapeout teams). Play the interface role between the users and the tool development teams and make sure the users’ needs are addressed in the tools and flow.
- 2 or 3 years hands-on experience on supporting verification, migration or extraction tasks.
- Knowledge of run set driving the verification/migration/extraction tasks a plus
- Knowledge of mask layout design
- Knowledge of Cadence/Skill
- Knowledge of C/C++, UNIX and Perl scripting languages
- Experience in tutorial developments and providing training to users a plus
- Good interpersonal & communication skills as this position requires extensive interaction with multiple design teams and the tool development teams.
Requires BSEE and 2 years experience or MSEE
Dataprep Group
Develop solutions for addressing DFM requirements in the chips targeting on improvements in yield and reliability. Develop run sets for incorporating some of the DFM rules in physical designs, both at block-level and chip-level. Work with foundries and EDA vendors, to implement and measure some of these DFM implementations in the chip design flow.
- 2 or 3 years hands-on experience using Synopsys Hercules or Mentor Calibre
- Experience in run set developments in Hercules or Calibre
- Experience with BindKey tools or something similar a plus
- Knowledge of mask layout design
- Knowledge of Cadence/Skill
- Knowledge of C/C++, UNIX and Perl scripting languages
- Experience with foundries on the BEOL and DFM/OPC activities.
- Good interpersonal & communication skills
Requires BSEE and 2 years experience or MSEE
Candidates must come from Microprocessor or large High Speed ASIC design teams
Experience in 130nm and 90nm.
Ideally looking for full-custom CAD engineers with circuit exp.
Strong (Cadence)Skill and/or Perl OO (Object Oriented) and/or C/C++ scripting a requirement.
· DFT lead with Tetramax and/or Fastscan experience; having defined test strategy for Microprocessors would be good.
· Strong Signal Integrity on-Chip and Off-Chip modeling (Power Supplies). Any kind of high speed modeling of Inductance a +
· Strong Low Power Clock design and/or Low jitter Clock design and/or PLL design (multiple designs)
· Pathmill and/or Primetime Timing Lead
· Strong Circuit lead with startup or who has started a design team from scratch/heavy methodology and time to market bent