Develop solutions for all aspects of Physical Design migration and verification for full custom digital and analog design. Implementation and development/automation of tasks for full chip physical design migration in addition to new methodology development and vendor tool evaluations and integration.

- 2-3 years hands-on-experience with physical migration (automatic layout modification) from process to process

Verification Group

Develop solutions for all aspects of VLSI physical design and verification for full custom digital and analog blocks and full chip. Perform development and validation of verification decks such as DRC (Design Rule Checking), LVS (Layout Versus Schematic), ERC (Electrical Rule Checking). Provide verification support for both full chip and block designers and develop infrastructures to automate the verification steps.

- 2 or 3 years hands-on experience with verification tasks such DRC, LVS and ERC.

- Experience in run set development with Synopsys Hercules tool or Mentor Graphics Calibre tool a plus

Extraction Group

Develop solutions for all aspects of VLSI physical design and extraction for full custom digital and analog blocks and full chip. Perform development and validation of extraction decks such as LPE (Layout Parasitic Extraction). Provide verification support for both full chip and block designers and develop infrastructures to automate the extraction steps including back annotation.

- 2 or 3 years hands-on experience with one or more of the following LPE tools: Star_RCXT, Calibre-XRC, quickcap, Raphael

- Good understanding of ASIC design flow, layout generation, circuit simulation, device physics and modeling. Familiar with up-to-date foundry process especially for BEOL.

- Good interpersonal & communication skills as this position requires extensive interaction with internal design team, verification teams and external tool vendors.

PDE Group

Responsible for the infrastructure for rolling out new tools and flows and provide physical design and verification/extraction support and address requirements from customers (layout designers, circuit designers and tapeout teams). Play the interface role between the users and the tool development teams and make sure the users’ needs are addressed in the tools and flow.

- 2 or 3 years hands-on experience on supporting verification, migration or extraction tasks.

- Knowledge of run set driving the verification/migration/extraction tasks a plus

- Good interpersonal & communication skills as this position requires extensive interaction with multiple design teams and the tool development teams.

Develop solutions for addressing DFM requirements in the chips targeting on improvements in yield and reliability. Develop run sets for incorporating some of the DFM rules in physical designs, both at block-level and chip-level. Work with foundries and EDA vendors, to implement and measure some of these DFM implementations in the chip design flow.

Circuit Design: San Diego

Strong (Cadence)Skill and/or Perl OO (Object Oriented) and/or C/C++ scripting a requirement.

· DFT lead with Tetramax and/or Fastscan experience; having defined test strategy for Microprocessors would be good.

· Strong Signal Integrity on-Chip and Off-Chip modeling (Power Supplies). Any kind of high speed modeling of Inductance a +

· Strong Low Power Clock design and/or Low jitter Clock design and/or PLL design (multiple designs)

· Strong Circuit lead with startup or who has started a design team from scratch/heavy methodology and time to market bent

SYSTEMS ENGINEER

* AN ACTIVE (CURRENT OR WITHIN PAST 2 YEARS) U.S. GRANTED SECRET SECURITY CLEARANCE.
* Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, Mechanical Engineering or Systems Engineering.
* Minimum of seven (7) years of related experience in Systems Engineering, Systems Design and experience with System Processes.
* Working knowledge of system analysis and test tools.
* Effective leadership of moderate to large and/or highly complex system development projects.
* Must be proficient in at least eleven of the specified systems skill areas.

System requirements definition/specification
HMI, GUI requirements
Functional allocation of system requirements to Subsystems and/or software, firmware and/or hardware configuration items
System safety, EMI/EMC, TEMPEST requirements
System environmental requirements
System reliability, maintainability, availability requirements
System logistics support, maintenance, operation, training requirements
System test requirements, requirements traceability
System design
System performance, timing, processing, sizing, power, etc. requirements generation and analyses
Operating system architecture
Database system architecture
Client-Server architecture
Hardware architecture
Software architecture
Software and hardware interface design requirements
Communications protocols
Analysis and design methodologies

SYSTEMS ENGINEERING MANAGER

SOFTWARE ENGINEER (Embedded Firmware Engineer)

* THIS POSITION REQUIRES AN ACTIVE (CURRENT OR WITHIN PAST 2 YEARS) U.S. GRANTED SECRET SECURITY CLEARANCE.
* Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering or related degree.
* Minimum of 5 years related experience.
* General Embedded Software Development experience
* Extensive C language experience.
* MIL-STD documents experience preferred.
* ARM Processor and/or 8051 Microprocessor experience preferred.
* KMU Experience preferred.
* Security documentation (Theory of Compliance, Theory of Design and Operation, CV Plans/Procedures, FSDA) development experience preferred.
* Embedded COMSEC software development experience preferred.
* COMSEC equipment development experience preferred.

Lead and Senior Product Development Engineer positions open. Salary: $90K - $110K.

Ensure the successful development and release to production of low distortion, low noise, high bandwidth / high-speed (up to 1 Ghz) amplifier products. These are IC’s. Must have strong lab skills. Must understand and have experience with amplifier chip sets to the transistor level. Responsible for developing evaluation analog/mixed signal boards used in data acquisition. Interpret measurements, run simulations, etc. Must have solid experience in characterization for analog mixed signal amplifier products.

The product line represents bipolar technology. The products include VGA’s, Digital VGA’s, OpAmp’s, Gain Difference Amps and rail-to-rail input/output amps.

Duties include silicon debug, bench characterization/evaluation, test hardware/software development. Interface with design, marketing and applications groups to effectively coordinate trim, test and bench characterization, and datasheet generation activities.

Requirements:
BSEE/MSEE with 5-15 years experience in Analog or Mixed-Signal IC Characterization, Test and Evaluation.

Strong circuits knowledge, good project management and communication skills a must.

Role: Team with microprocessor architects and other array designers to study cache implementations for a low power embedded processor.

Skills/Experience Candidate must be familiar with static CMOS circuit structures and dynamic circuit structures.

Must have a minimum of 7 years experience in: CMOS circuit design, using Cadence design tools (Composer, Virtuoso), using circuit analysis tools (Spice or equivalent).

Must have a minimum of 7 years in completing and/or directing layout work (DRC/LVS).

Candidate must be well versed in advanced cache solutions and the associated power implications, both active and standby. Candidate should be familiar with primary leakage mechanisms for DSM processes and also circuit strategies for minimizing them. Candidate should also be experienced with TLB circuit

Role: Team with processor logic designers to propose and analyze various custom circuit solutions for critical data path elements. Typical circuits will include: 32 bit adders, multiplier circuit elements, and register arrays.

Skills/Experience: Must have a minimum of 5 years experience in: CMOS circuit design, using Cadence design tools (Composer, Virtuoso), using circuit analysis tools (Spice or equivalent).

Must have a minimum of 5 years in completing and/or directing layout work (DRC/LVS).

Designer should be familiar with standard circuit approaches for CPU adders and the associated design trade offs. Designer should be familiar with primary leakage mechanisms for DSM processes and also circuit strategies for minimizing them.

Deliver blocks that meet power, timing and area constraints. Evaluate power saving techniques from circuit point of view. Interface with other groups regarding timing closure, support, etc. Floor-planning. Work closely with architect regarding feasibility studies and circuit issues. Provide timing models for top level effort.

Spice, simulation tools. Experience with taping out chips and layout supervision. Implementation background such as driving layout, DRC, LVS. Familiar with static timing tools and timing closure.

Additional Skills Experience with Cadence and Synopsys tools a plus. Excellent verbal and written communications with ability to work in a team environment.

Role: Design high-performance, low-power on-chip memory controllers for wireless application using various types of memory devices.

Skills/Experience Extensive Knowledge of memory devices including SDRAM and DDR/DDR2 memories. Familiarity with Amba AXI/AHB or CoreConnect Bus structures. Solid VHDL/Verilog coding skills. Familiarity with System C or C++. Thorough knowledge of both deterministic and random verification methodologies.

Summary of duties and required experience :
Tactical and strategic support of RF Wireless IC Products. Technical support of customer designs. Management of a small group of applications engineers. Customer visits to support design-ins and new product definitions. Author app no tes, articles, white papers, trade-show papers, training material and datasheet applications. Systems Analysis of WCDMA an GSM/EDGE air interfaces for new product definition. Develop applications circuits, reference designs and evaluation boards. Competitive Analysis. BSEE or equivalent, 3 to 5 years of design or applications experience with RF/IF components. Good communication skills.

Specific Responsibilities / Duties:
·    Provide technical support to customers to assist in the design-in of components.
·    Manage a small group of applications engineers.
·    Travel to promote RF products and to facilitate new product research.
·    System-Level Analysis of RF/IF Signal Chains.
·    Supply Technical Input to Product Definitions (functionality, target specifications, pin-out, concept datasheet, etc)
·    Develop Reference Designs for new pr oducts.
·    Author White Papers in support of new ideas.
·    Attend Trade Shows and present papers at conferences.
·    Write application notes and datasheet applications section for new products.
·    Design evaluation boards.
·    Construct technical training material for customers and FAEs.
·    Analysis of competitors' products.
Previous Experience & Education Required
·    BSEE required
·    5 years of design or applications experience with RF/RF components and/or handset PAs.
·    Experience in presenting and good communications skills
·    Good customer skills
·    Agilent ADS a plus.

This R&D center develops image processing applications for: image acquisition, 3D rendering, 360 degree imaging, biometrics, facial recognition, and video surveillance.

Please call Todd Lyon at 716-751-6345 or email your resume to tlyon@jobjungle.net

Located in San Diego

Migration Group

Verification Group

Extraction Group

PDE Group

Circuit Design: San Diego

SYSTEMS ENGINEER

SYSTEMS ENGINEERING MANAGER

SOFTWARE ENGINEER (Embedded Firmware Engineer)